An Area Efficient Approach: Comparative Analysis of Multiplier Circuits

Low voltage low power programmable logic gate based on SE-MOSFET

An 8-Bit Full-Adder Implementation Using Single Electron Tunneling (SET) Technology.

Design and Implementation of Advanced Encryption Standard by New Substitution Box in Galois Field (𝟐𝟖)

CMOS LOGIC FAMILIES FOR VLSI DESIGN

CMOS LOGIC FAMILIES FOR VLSI DESIGN

DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR

Design and Implementation of Digital Delay Line Integrator (DDLI) using FPGA and DSP

Design of Low Voltage 1st Order 3-Bit Quantizer SR ΔΣ Modulator Using SR Op-Amp