Improvements in the performance of integrated circuits include scaling of transistor size and reduction of operating voltage. Smaller area and power dissipation have also taken care of for fabrication of high performance. Optimizing the power consumption, speed, area and delay of the multiplier are a major issue. In this article, the best solution to this problem is determined. As we know, Adders and Multipliers are key components of many high performance systems. By designing different multipliers, implementing their components is better to choose an option between CSL, DPL & CPL adders in fabricating different systems. This article focuses on the comparison between two algorithms for multiplication, Array and Wallace Tree. The implementation of these algorithms is performed by designing (4 ×4and8 ×8) bit multiplier blocks in 0.18μ C MOS technology using EDA Tanner v.13 (evaluation version) framework tools. Furthermore, the 8-bit multipliers on GDI adder cells are compared using EDA Tanner. Multiplier design in this article provides the low power requirement and presents an area efficient approach. Moreover, number of transistors is also less as compared to CMOS for any design.