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30808

Design and Implementation of Digital Delay Line Integrator (DDLI) using FPGA and DSP

Article

Last updated: 24 Dec 2024

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Abstract

In the present work, the design and implementation of digital delay line integrator (DDLI) which is a common radar signal processing technique is proposed. The design and implementation is achieved using two of the new developed digital hardware platforms: Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs). Comparison between these developed digital hardware platforms based on the implemented DDLI is introduced. This is done to find out the aspects of choosing which platform is the best for implementing certain radar signal processing technique.

DOI

10.21608/iceeng.2012.30808

Authors

First Name

Saad

Last Name

El gayar

MiddleName

M.

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Orcid

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First Name

Fathy

Last Name

Ahmed

MiddleName

M.

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-

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-

Orcid

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First Name

Nabil

Last Name

Mikhail

MiddleName

G.

Affiliation

-

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-

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Volume

8

Article Issue

8th International Conference on Electrical Engineering ICEENG 2012

Related Issue

5272

Issue Date

2012-05-01

Receive Date

2019-04-28

Publish Date

2012-05-01

Page Start

1

Page End

9

Print ISSN

2636-4433

Online ISSN

2636-4441

Link

https://iceeng.journals.ekb.eg/article_30808.html

Detail API

https://iceeng.journals.ekb.eg/service?article_code=30808

Order

62

Type

Original Article

Type Code

833

Publication Type

Journal

Publication Title

The International Conference on Electrical Engineering

Publication Link

https://iceeng.journals.ekb.eg/

MainTitle

Design and Implementation of Digital Delay Line Integrator (DDLI) using FPGA and DSP

Details

Type

Article

Created At

22 Jan 2023