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33547

DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

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Last updated: 24 Dec 2024

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Abstract

ABSTRACT:
In this paper, we present developed design procedures for a pipelined Advanced
Encryption Standard [AES] encryption algorithm using Field Programmable Gate Array
[FPGA].The design procedures starting from entering the design parameters until
functional simulation and testing have been introduced in this paper. System throughput
of 1.408Gbps has been achieved, whereas the published results for similar systems are
much less than this rate [4-7].

DOI

10.21608/iceeng.2006.33547

Keywords

FPGA, AES, VHDL, Encryption, decryption

Authors

First Name

Alaa El Din

Last Name

Rohiem

MiddleName

-

Affiliation

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Email

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City

-

Orcid

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First Name

Kamel

Last Name

Hassan

MiddleName

Mohamed

Affiliation

-

Email

-

City

-

Orcid

-

First Name

Ahmed

Last Name

El-Amin

MiddleName

M.

Affiliation

-

Email

-

City

-

Orcid

-

Volume

5

Article Issue

5th International Conference on Electrical Engineering ICEENG 2006

Related Issue

5615

Issue Date

2006-05-01

Receive Date

2019-05-28

Publish Date

2006-05-01

Page Start

1

Page End

24

Print ISSN

2636-4433

Online ISSN

2636-4441

Article File

ICEENG_Volume 5_Issue 5th International Conference on Electrical Engineering ICEā€¦.pdf

PDF . 359.6kB

Link

https://iceeng.journals.ekb.eg/article_33547.html

Detail API

https://iceeng.journals.ekb.eg/service?article_code=33547

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Type

Original Article

Type Code

833

Publication Type

Journal

Publication Title

The International Conference on Electrical Engineering

Publication Link

https://iceeng.journals.ekb.eg/

MainTitle

DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

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Article

Created At

22 Jan 2023