Architecture for the BIST Boundary Scan

A NEW DESIGN FOR COMPRESSION TECHNIQUE FOR TESTABILITY DESIGN

DESIGN AND IMPLEMENTATION OF NEW AUTOMATIC TESTING SYSTEM FOR DIGITAL CIRCUITS BASED ON THE SIGNATURE ANALYSIS

Design for Testability of Circuits and Systems; An overview

NEW AUTOMATIC TESTING ARCHITECTURE FOR INTEGRATED CIRCUITS

Design for Testability Technique for Microcontroller

COMPUTER AIDED DESIG: COMPUTER AIDED TESTING MODELLING TECHNIQUE

A NEW SINGLE TEST PATTERN GENERATOR FOR PSEUDOEXHAUSTIVE TESTING

FPGA implementation of the portable automatic testing system for digital circuits

New Digital Testing of Analogue Circuits