With the advance in LSI/VLSI technology, the increasing inaccessiblity and density of the oil-Cults and shortage of I/O ports for test purposes make testing more difficult and complex. This complexity in testing can be alleviated by making the design at Smallest-Repair-Replaceable-Unit (SRRU) level a testable design. The aim of the testable design concepts is to achieve, control, observation and isolation down to SRRU (chip) level. These concepts should be available by the construction of testability design to prevent the faulty propagation from one chip to another and to attain the highest degree of testing capability. One of the techniques to achieve the testability design concepts is the compression technique. The established design for this technique has some problems which cannot be avoided, for example, it cannot provide isolation between the chips at SRRU level in TM (Test Mode), and at the same time to be used in system in OM (Operation Mode). Furthermore. the established design requires a much longer test application time. To alleviate the effects of these problems and to obtain more reliable results, a new design for compression technique will be proposed.