ABSTRACT
Integrated circuits (ICs) are reaching complexity that was hard to imagine. ICs incorporating
hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc.,
are in high demand. Obviously, designing such complex circuits poses real challenges to
engineers. Certainly, no relief comes from the competitive marketplace, with increasing
demands for a very narrow window of time (time-to-market) in engineering a ready product.
Therefore, a systematic and well-structured approach to designing ICs to be testable is a must.
With the growth in complexity of very large scale integration (VLSI) circuits, test generation
for circuits is becoming increasingly difficult and time consuming. Even though the
computing power and resources have multiplied dramatically over last few decades, an
increasing number of memory elements in VLSI circuits require more effective and powerful
sequential test generators. This paper is represented to review concepts and techniques for
testing electronic circuits and systems as part of a lecture review.
This covers various testing and design-for-test (DFT) techniques starting from (Automatic
Test Equipment) ATE basics (definition, construction and types). Exploring testing strategies
for digital combinational and sequential circuits, and introduces a comparative study between
the common fault models. Finally the paper ends with design for testability guiding rules and
possible challenges and difficulties that need development and research in the testing
problem.