DESIGN AND IMPLEMENTATION OF NEW AUTOMATIC TESTING SYSTEM FOR DIGITAL CIRCUITS BASED ON THE SIGNATURE ANALYSIS

NEW AUTOMATIC TESTING ARCHITECTURE FOR INTEGRATED CIRCUITS

FPGA implementation of the BIST intellectual property core for SRAM chips on the board

Design for Testability of Circuits and Systems; An overview

New Digital Testing of Analogue Circuits

Safety Critical FPGA Design

FPGA implementation of OFDM physical layer

A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR

A NEW SINGLE TEST PATTERN GENERATOR FOR PSEUDOEXHAUSTIVE TESTING

A NEW DESIGN FOR COMPRESSION TECHNIQUE FOR TESTABILITY DESIGN