D Flip Flop with Different Technologies

Design and Simulation of 140 dB Dynamic Range and 20 uVrms Readout Noise CMOS Image Sensor

Toward high-speed level-crossing ADCs

CMOS LOGIC FAMILIES FOR VLSI DESIGN

CMOS LOGIC FAMILIES FOR VLSI DESIGN

Hardware Algorithm for Static and Dynamic Rams Testing.

A Charge-Accumulation Based High-Performance CMOS Circuit

Design and simulation of 140 dB dynamic range and 20 uVrms readout noise COMS image sensor

Trends in CMOS image sensor design and technology

DESIGN AND IMPLEMENTATION OF A DIGITAL RADIO FREQUENCY MEMORY