This paper provides the design, simulation and
implementation of a very wide dynamic range and a low readout
noise CMOS image sensor (CIS) with high sensitivity by using a
diode connected transistors in parallel with floating diffusion
node and sensor output. The sensor is simulated, designed and
implemented in a 130 nm CMOS technology using cadence tool.
The area of the proposed pixel reaches to 3 um x 3 um and
consists of seven NMOS transistors and one capacitor. The
readout circuit has the following parameters as very low output
noise of 20 uVrms with a 5 MHz bandwidth for pixel circuitry.
Power dissipation of 10 uW was achieved at an operation voltage
of 1.6 V for pixel circuitry. The proposed sensor has good
features of low noise and a 140 dB wide dynamic range due to the
diode connected transistor configuration that has been used. This
paper provides the effect of adding a diode connected transistors
M7 and M8 on an increasing dynamic range of CMOS image
sensor to 140 dB and reducing its readout noise to 20 uVrms. Also,
this paper provides a mathematical simulation of noise model of
CIS using Matlab and cadence.