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199897

D Flip Flop with Different Technologies

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Last updated: 23 Jan 2023

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Abstract

This article explains a new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique,
PowerPC, DSTC, and HLFF. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low
complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of
devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF as compared to other methods. The performance
is carried out by HSPICE simulation with 180 nm & 90 nm CMOS technology.

DOI

10.21608/aeta.2014.199897

Keywords

 D flip-flop, low power, Gate-Diffusion-Input (GDI) technique, PowerPC, DSTC, and HLFF

Authors

First Name

Amit

Last Name

Grover

MiddleName

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Affiliation

Department of Electronics & Communication Engineering, S.B.S State Technical Campus Ferozepur, Punjab, India

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First Name

Sumer

Last Name

Singh

MiddleName

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Affiliation

Department of Electronics & Communication Engineering, Government Polytechnic College, Ferozepur, Punjab, India

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Volume

3

Article Issue

1

Related Issue

28180

Issue Date

2014-01-01

Receive Date

2021-10-17

Publish Date

2014-01-01

Page Start

6

Page End

11

Print ISSN

2090-9535

Online ISSN

2090-9543

Article File

AETA_Volume 3_Issue 1_Pages 6-11.pdf

PDF . 1.9MB

Link

https://aeta.journals.ekb.eg/article_199897.html

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https://aeta.journals.ekb.eg/service?article_code=199897

Order

199,897

Type

Original Article

Type Code

2,017

Publication Type

Journal

Publication Title

Advanced Engineering Technology and Application

Publication Link

https://aeta.journals.ekb.eg/

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Article

Created At

23 Jan 2023