During the reading of one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier. The net result is that the higher voltage will rise to VDD while the lower one will decrease to 0 V. Simulation results for the 0.13 µm CMOS technology with VDD=1.2 V reveals that about 40% of the read access time is associated with the sense amplifier operation in addition to the area required by each sense amplifier for each column in the memory array. In this paper, a novel current-mode readout technique for use with DRAM cells is presented. This method depends on converting the bitline voltage to a current to be compared with a reference current. The positive-feedback effect of the current comparator then comes into action with the result that one of its outputs will be the required output data taken at a much smaller parasitic capacitance compared with the bitline parasitic capacitance. Simulation results for the 0.13 µm CMOS technology show that about 10% of the read access time can be saved. The, the power-delay products in case of reading "1" (the worst case from the point of view of PDP) are 388.5 fJ and 188 fJ for the conventional and proposed schemes, respectively