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33505

An Implementation of the Run-Length Decode Algorithm using FPGA

Article

Last updated: 04 Jan 2025

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Abstract

Abstract:
This paper presents a real time implementation of Run-Length Decode (RLD) using FPGA as
one of image decompression algorithms. The RLD algorithm is the decoder of the Run-
Length Encode. RLD can be implemented either on commercial DSP or as an ASIC but due
to the huge development in the FPGA field, it is recommended to use the FPGA technology.
The design steps from design entry to files which are needed for the download process are
developed. Also, the method of testing the downloaded design is explained.

DOI

10.21608/iceeng.2006.33505

Keywords

Run-Length Decode, FPGA, Image compression

Authors

First Name

Gouda

Last Name

Salama

MiddleName

Ismail

Affiliation

Ph.D., Egyptian Armed Forces.

Email

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City

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Orcid

-

First Name

Fawzy

Last Name

Hassan

MiddleName

ELtothamy

Affiliation

Ph.D., Egyptian Armed Forces.

Email

-

City

-

Orcid

-

First Name

Ramy

Last Name

Bahy

MiddleName

Mohammed

Affiliation

M.Sc., Egyptian Armed Forces.

Email

-

City

-

Orcid

-

First Name

Sameh

Last Name

Ibrahim

MiddleName

shawky

Affiliation

B.Sc., Egyptian Armed Forces.

Email

-

City

-

Orcid

-

Volume

5

Article Issue

5th International Conference on Electrical Engineering ICEENG 2006

Related Issue

5615

Issue Date

2006-05-01

Receive Date

2019-05-28

Publish Date

2006-05-01

Page Start

1

Page End

8

Print ISSN

2636-4433

Online ISSN

2636-4441

Article File

ICEENG_Volume 5_Issue 5th International Conference on Electrical Engineering ICEENG 2006_Pages 1-8.pdf

PDF . 296.4kB

Link

https://iceeng.journals.ekb.eg/article_33505.html

Detail API

https://iceeng.journals.ekb.eg/service?article_code=33505

Order

8

Type

Original Article

Type Code

833

Publication Type

Journal

Publication Title

The International Conference on Electrical Engineering

Publication Link

https://iceeng.journals.ekb.eg/

MainTitle

An Implementation of the Run-Length Decode Algorithm using FPGA

Details

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Article

Created At

22 Jan 2023