New applications of digital embedded control systems require more advanced techniques that can fulfill increasing control requirements and to meet control constraints, such as reaching RT deadlines, while trying to achieve additional tasks like
auto-tuning of the parameters of control algorithm, conducting diagnostic-based operations or executing a fault-tolerance algorithm. Hence, Multiprocessors System on Chip (MPSoC) has been proposed as a promising solution. The main purpose of this paper is to put a step towards enhancing the legacy digital PID control algorithm by exploiting its inherent parallelism. We propose a direct-mapping design of the sequential digital PID to a custom Quad-Core Master-Slave MPSoC design, built-up using an enhanced FPGA Soft-Core microcontroller.