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302717

RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study

Article

Last updated: 04 Jan 2025

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Tags

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Abstract

RISC-V is an open Instruction Set Architecture (ISA) that is expected to dominate the market in the next few years. It is forecasted that market will consume 62.4 billion RISC-V CPU cores by 2025. In this project a RISC-V core is physically implemented as an ASIC using Nangate Open Cell Library 45nm PDK and its performance is compared to a 45nm based Spartan 6 FPGA implementation.

DOI

10.21608/iugrc.2022.302717

Keywords

FPGA, ASIC, RISC-V

Authors

First Name

Mohammed

Last Name

El-desouky

MiddleName

-

Affiliation

Nanotechnology and Nano electronics Engineering Department , UST at Zewail City 12578 Ahmed Zewail Street, October Gardens 6th of October City, Giza, Egypt.

Email

s-mohammed.eldesouky@zewailcity.edu.eg

City

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Orcid

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Volume

6

Article Issue

6

Related Issue

41697

Issue Date

2022-09-01

Receive Date

2023-06-08

Publish Date

2022-09-01

Page Start

1

Page End

3

Article File

IUGRC_Volume 6_Issue 6_Pages 1-3.pdf

PDF . 583.4kB

Link

https://iugrc.journals.ekb.eg/article_302717.html

Detail API

https://iugrc.journals.ekb.eg/service?article_code=302717

Order

302,717

Type

Original Article

Type Code

762

Publication Type

Journal

Publication Title

The International Undergraduate Research Conference

Publication Link

https://iugrc.journals.ekb.eg/

MainTitle

RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study

Details

Type

Article

Created At

24 Dec 2024