A higher data rate with lower intersymbol interference (ISI) and intercarrier interference (ICI)
are the main features provided by Filter bank multi-carrier (FBMC) modulation technique to
be the most candidate for 5G wireless networks. Although the different advantages of FBMC
systems, it suffers from the higher power consumption and complexity of the structure, as a
result of using fast Fourier transform/ inverse fast Fourier transform (FFT/IFFT) processors
with a high order polyphase filter network in both transmitter and receiver. This paper
presents a complete analysis, design, and implementation of a proposed low power FBMC
transceiver architecture for a different number of multi-users or subscribers. The suggested
method aims to reduce power consumption and area resources by reducing the complexity of
the FFT (2𝑛 Points) processor by using a feedback loop with a (𝑛) points FFT core. Also, the
design of FIR filters is based on distributed arithmetic (DA) algorithm in which all
multiplications and additions are replaced by a table and a shifter. The design and
implementation are done using a Xilinx system generator tool and spartan-6 field
programmable gate array (FPGA) board. The proposed implementation method presents a
reduction in resources by 15 % compared to conventional implementation.