The design of the placement and routing for an FPGA (whether it's a traditional or coarse grained field programmable gate arrays) is very important process, requiring the care about the flexibility with silicon efficiency. With the motivation growing towards embedding FPGAs into SoC (system on chip) designs, final requirements for the FPGA architectures becomes more critical. The identification of a routing channel requires determining the number of routing paths (tracks), the length of the segments in those paths, and the positioning of the breaks on the paths. We have developed an optimal algorithm to alleviate the routing and placement problem. This research focuses on the maximization of the flexibility and expandability to achieve the final placement with the convenient path(s) (routing). The optimal algorithm finds a solution provided the problem meets a number of restrictions such as busy or faulty path(s) in the routing process and applying the partial configuration to reduce the configuration time to achieve the required placement.