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147060

A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.

Article

Last updated: 04 Jan 2025

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Subjects

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Tags

Electronics and Communications Engineering

Abstract

A fully differential CMOS sample and hold circuit (S/H) in current mode double sampling technique, gives a factor of two increase in the sampling rate while maintaining comparable power consumption and circuit complexity in comparison with the conventional S/H configuration. A precise current mirror circuit with low input impedance is adopted. A fully differential configuration for placing the switches were used to cancel the sample switches feed-through error. Also, the clock controlling the sample switches is boosted so as to make their on resistance low. The circuit is designed and simulated in 0.5 µm CMOS technology using BSIM3v3 device parameters. Simulation results shows 10-bit operation at the sampling rate of 80  sample/sec with 10mW power dissipation at 3 V supply.

DOI

10.21608/bfemu.2021.147060

Authors

First Name

Hamed

Last Name

El-Simary

MiddleName

-

Affiliation

Electronics Research Institute., Cairo., Egypt.

Email

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City

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Orcid

-

Volume

25

Article Issue

4

Related Issue

21256

Issue Date

2000-12-01

Receive Date

2000-10-08

Publish Date

2021-02-07

Page Start

42

Page End

49

Print ISSN

1110-0923

Online ISSN

2735-4202

Article File

BFEMU_Volume 25_Issue 4_Pages 42-49.pdf

PDF . 85.7kB

Link

https://bfemu.journals.ekb.eg/article_147060.html

Detail API

https://bfemu.journals.ekb.eg/service?article_code=147060

Order

3

Type

Research Studies

Type Code

1,205

Publication Type

Journal

Publication Title

MEJ. Mansoura Engineering Journal

Publication Link

https://bfemu.journals.ekb.eg/

MainTitle

A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.

Details

Type

Article

Created At

22 Jan 2023