The phase-locked loop (PLL) is the critical clock module in the System on Chip (SoC). PLL is a very complex process since it includes various parameters which are directly related to the performance of the PLL. Fast locking and low power consumption are the most important parameters in Digital PLL (DPLL). In this paper, a DPLL has been proposed and simulated to satisfy the requirements of RF applications. Digitally Controlled Oscillator (DCO) is the core of the DPLL which affects its overall performance, so an enhanced DCO structure has been proposed in a ring topology. The delay element of the ring oscillator is a Bulk Driven (BD) inverter which offers a promising enhancement in power consumption. The proposed DPLL scheme has been simulated using TSMC 65nm CMOS technology. Using 0.4V BD XNOR gate as a delay element of the ring oscillator, the output power is reduced to 61.74 µw, also the DPLL has produced 409MHz output frequency with a high speed of 23 ns locking time.