A time-based serial data link architecture that involves dual modulation Pulse Position Modulation approach (DMPPM) is presented in this paper. In the proposed approach, both the rising and falling edges of the input clock signal are modulated independently. Using the proposed approach allows increasing the total number of transmitted bits without significantly affecting the modulated signal bandwidth. A 6-bit 4.8 Gb/s DMPPM link design example has been designed and simulated based on the proposed approach in 130nm CMOS technology. An 800MHz has been used as an input clock signal. The simulation results and a comparison between the proposed link and other serial links are presented. The power consumption of the transmitter and the receiver circuits are less than 100mW.