The theory, design, imple -nentation and evaluation of Two-Phase Dynamic FET Logic (TPDL), a logic fami y that is compatible with the existing Complementary Gallium Arsenide (CGaAs) fabrication process and design tools, is documented. Several different logic functions have been implemented in both TPDL and static logic. A performance comparison between the TPDL and static logic circuits is also performed. TPDL circ Jits are much faster than the static circuits performing the same function becaus a the former do not use PFETs for logic expression evaluation, only for precharging. Also, TPDL circuits co: •sumes less power than static circuits because they have no short-circuit current and a reduced leakage current. The maximum operating frequency of the TPDL circuits is 2.38 GHz and they have the lowest poorer-delay product ever reported in this technology (0.01mW/gate/MHz).