In this work we present a proposed High-Level Synthesis (HLS) methodology for dedicated Digital Signal Processing (DSP) architectures. Starting from a purely behavior description of a DSP algorithm, the HLS subtasks namely: the Scheduling, the Allocation, and the Binding are performed to generate an optimized Register Transfer Level (RTL) data path structure which implements the intended behavior while satisfying the .timing constraints. The Scheduling and the Allocation subtasks are solved simultaneously in terms of an Integer Linear Programming (ILP) feasibility model. The Binding subtask is solved using a Weighted Bipartite Matching (WBM) algorithm. A 4-point FIR filter is used to demonstrate our methodology in a step wise fashion, from the initially specified behavior to the finally synthesized structure. Simulation results have proved that the finally synthesized data path is truly implementing the initially specified behavior and satisfying the timing constraints.