Abstract:
This paper presents a new low voltage low power current mode threshold logic (CMTL)
circuits using DGMOSFETs. The ultimate feature of the double gate transistor is using
the top and bottom gates in the design of the logic circuits that reduces the number of
the transistors. The total number of the transistors required to implement the CMTL
circuits and the power dissipation is almost reduced by half by using the DGMOSFET.
OR, AND, MAJ logic gates are designed using DGMOSFETs and simulated using
HSPICE. The results for the proposed 45 nm DGMOSFET logic circuits with 1 V
supply voltage show low power dissipation, smaller power delay product and less
number of device.