The demand for efficient, real time video cryptography systems has become more prominent in our life, especially for military and sensitive-civilian applications. FPGA implementation of video cryptography systems is suitable for both video and cryptography processes due to video data rate, flexibility to design modifications, and cryptography algorithm agility. In this paper, a bulk video cryptography system using AES (Advanced Encryption Standard) is designed and implemented on low cost FPGA Xilinx Spartan-III™. Bulk encryption is used to encrypt both video data and video synch to increase the cryptanalysis complexity for intruders. The design is implemented on different stages; camera interface, video frame grabber, VGA monitor interface, SDRAM controller, crypto processor, and communication channel interface. The design has been tested first using a generated video pattern, and using external composite PAL/NTSC video camera source. The design is implemented for XC3S1000 and the results were significant for speed and area, it reached 77.6 Mbytes/sec. data throughput that fulfills the minimum requirements of colorful, 30 FPS video data rate of 27 Mbytes/sec., and the design
occupies 3,738 slices (48 % of chip size).