The demand for efficient, real time video cryptography systems has become more prominent in our life, especially for military and sensitive-civilian applications. The proposed system design was constrained in both area and speed in order to fulfill the requirements for real time video signals with limited hardware resources. Using Field Programmable Gate Array (FPGA) for the system implementation is suitable for both video and cryptography processes due to video data rate, flexibility to design modifications, and cryptography algorithm agility. The design strategy was based on making use of all available pre-designed, pre-verified cores for low cost Xilinx Spartan III XC3S1000-ft256 FPGA chip. In this system, only active video data are encrypted with (Rijndael) Advanced Encryption Standard (AES) crypto algorithm and a self-synchronized cipher key mechanism based on the embedded video Timing Reference Signals (TRS) was designed to overcome the security leakage in Electronic Codebook (ECB) mode and to reduce the possibilities of cryptanalytic attacks which are used to recover the encryption key like brute force attacks. The design is tested first using an internally generated video pattern, then using external composite video camera source. The design implementation results were significant for speed and area, it reached 59.044 Mbytes/sec. data throughput that fulfills the minimum requirements of colorful, 30 FPS video data rate of 27 Mbytes/sec., and the design occupies 4,007 slices (52% of chip size).