in this paper, design and generation of 50 kHz and 200 kHz is proposed using FPGA VHDL codes. The type of FPGA Board used in this project is Altera DE1-SoC. Altera DE1-SoC development kit comprises of Cyclone V SoC 5CSEMA5F31C6 device and has 85K Programmable Logic Elements which are more than sufficient for this project. The trigger starts the process of generation of pulses of desired frequency and duration. The pulses are generated through Pulse Width Modulation (PWM) technique. The designed pulses have PRF of 10 Hz to get maximum depth of 75 m and have pulse length of 0.4 mS to get good resolution of 0.3 m. The bandwidth designed is 5 kHz for 50 kHz and 200 kHz signals. Codes are flexible to generate other signals with different frequencies and different PRF. The simulation is done using Modelsim software which is also a tool form Altera used for simulation and debugging of the digital logic. It is used to check the timing requirements. Their combination results are efficient to be amplified and then transmitted using transducer.