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27208

AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA

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Last updated: 04 Jan 2025

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Abstract

This paper presents a real time implementation of Run-Length Encode (RLE) using FPGA as one of image compression algorithms. The RLE algorithm can be implemented either on commercial DSP or as an ASIC but due to the huge development in the FPGA field, it is recommended to use the FPGA technology. The design steps from design entry to files which are needed for the download process are developed.

DOI

10.21608/asat.2011.27208

Keywords

Run-Length Encode, FPGA, Image compression

Authors

First Name

Gouda

Last Name

Salama

MiddleName

I.

Affiliation

Egyptian Armed Forces.

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Orcid

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First Name

Fawzy

Last Name

Hassan

MiddleName

ELtohamy

Affiliation

Egyptian Armed Forces.

Email

-

City

-

Orcid

-

First Name

M.

Last Name

Sharrawy

MiddleName

-

Affiliation

Faculty of Computers and Information, Helwan University, Egypt.

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Orcid

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First Name

Ramy

Last Name

Bahy

MiddleName

M.

Affiliation

Egyptian Armed Forces.

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-

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-

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-

Volume

11

Article Issue

ASAT Conference, 17-19 May 2005

Related Issue

4906

Issue Date

2011-05-01

Receive Date

2019-02-14

Publish Date

2011-05-01

Page Start

947

Page End

954

Print ISSN

2090-0678

Online ISSN

2636-364X

Article File

ASAT_Volume 11_Issue ASAT Conference, 17-19 May 2005_Pages 947-954.pdf

PDF . 1.4MB

Link

https://asat.journals.ekb.eg/article_27208.html

Detail API

https://asat.journals.ekb.eg/service?article_code=27208

Order

59

Type

Original Article

Type Code

737

Publication Type

Journal

Publication Title

International Conference on Aerospace Sciences and Aviation Technology

Publication Link

https://asat.journals.ekb.eg/

MainTitle

AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA

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Article

Created At

22 Jan 2023