Conventional testing methods of digital systems are not practical for microprocessors due to: - Their high density of integration ( VLSI) , lack of information about their internal physical structure , internal test points are not accessible , impossibility of inserting new test points in an integrating chip with a limited number of external leads (pins ) and due to the nonprecision of hardware failure modes of new technologies such as CMOS,bipolar, etc. - Moreover, the conventional test methods have two serious limitations concerning their application for the verification of LSI circuits: - They consider the SSI components (gates, flip-flops, ....) as the primitive test elements. - They apply fault models based primarily on the s-a-O & s-a-1 model which associates faults to the connections between those basic elements. Bit-sliced microprocessors represent an important class of LSI components (microprogrammable ). A microprogrammed system can be generally tested by a suitable microprogram added to its normal operation microprograms This paper presents a methodology for generating a test microprogram for one of the recent powerful bit-sliced microprocessors (the superslice Am 2903).The test procedure is based on a fault model that takes into account a large variety of faults encountered with such microprocessors . The fault model is formulated at: a higher level in terms of functional modules such as the ALU, memory and multiplexers. The derived test is nearly — minimal and its execution does not speed down the system operation