Testing for delay and CMOS stuck-open faults requires two-pattern tests. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-pattern testing should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include autonomous linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage with the optimal test lengths.
In this paper, the two-pattern test capabilities of LFSR/SRs are explored using transition coverage as the metric. The necessary and sufficient conditions to ensure complete transition coverage for LFSR/SRs are derived. The theory developed here identifies all LFSR/SR TPGs that determine the complete transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Based on the necessary and sufficient conditions, two-pattern testing have been developed. Experiments indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage with the optimal shortest test lengths.