Low dropout linear voltage regulators are analog circuit blocksthat play an important role in power delivery process and prevent a system from fluctuations in the supply rails.There is a high demand on using LDO regulator in system-on-chip (SOC) applications, given their inherently noisy environment.This work presents a design of low dropout voltage regulator (LDO) to satisfy desiredparameters. Basic design parameters of the proposed LDO CMOS circuit are introduced. The proposed circuit is designedto achieve a low quiescent current and dropout voltage as well as large PSRR value as possible, while maintaining the stability is paramount.Simulation results of the proposed circuit using 180 nm process CMOS technology and its corner analysis are presented. The simulation of the proposed LDO design achieveslow quiescent current in the range of microamperes.