This paper presents a VHDL-AMS model for the simulation ofsingle-electron transistor (SETs) using VHDL-AMS (Very High speed Descriptive Language-Analogue and Mixed signal). The model is based on the SPICE macro-model. From the SPICE macro-model simple relations were derived which are suitable for VHDL-AMS. The proposed model can fully analyze the circuits containing analogue and digital applications with the advantage of concurrency of VHDL-AMS systems. The proposed model can describe the IDS-VDS characteristics ofSET and is applied to a Single-Electron NOR gate circuit. The resulting voltage transfer characteristics agreed with the results obtained from the SPICE macro-model. The model overcomes the difficulties associated with other techniques based on Monte-Carlo simulation