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Motion Estimation (ME) is vital element in video coding as it reduces temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. Hexagonal search algorithm is one of Fast Block Matching Algorithms (FBMAs) which belongs to block based motion estimation. This paper presents a hardware design of hexagonal search algorithm and its implementation on FPGA. We specified, simulated and synthesized the design with VHDL description. The proposed design is implemented on a "virtex5" FPGA using xc5vlx30-3ff676 component. Our simulations confirm the functionality of the algorithm using Modelsim (version XE 6.3.4) simulator. When our design was synthesized on xc5vlx30-3ff676, we obtained the following results for area and clock frequency: 6810 LUT and 65,892MHz respectively.
DOI
10.21608/mjeer.2010.66515
Keywords
Motion Estimation (ME), HEXagonal Based Search algorithm (HEXBS), Fast Block Matching Algorithm (FBMA), Sum Absolute Difference (SAD), Processing Element (PE)
Authors
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Eng. Dept, NRC, Atomic Energy Authority, Inshas, Egypt.
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Eng. Dept, NRC, Atomic Energy Authority, Inshas, Egypt.
Email
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Faculty of Electronic Engineering, Menoufiya University, Menouf, Egypt
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https://mjeer.journals.ekb.eg/article_66515.html
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https://mjeer.journals.ekb.eg/service?article_code=66515
Publication Title
Menoufia Journal of Electronic Engineering Research
Publication Link
https://mjeer.journals.ekb.eg/
MainTitle
Hardware Design of Hexagonal Search Algorithm